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MH89626C
OPS/DID SLIC Preliminary Information
Features
* * * * * * * * * * * Transformerless 2-4 wire conversion Constant current with constant voltage fallback for long loops Long length capability (R Loop > 1850) Input impedance 200 + 560 // 0.1F (MH89626C-02) 200 + 680 // 0.1F (MH89626C-04) Ring trip filter with auto ring trip Three relay drivers Built-in Tip/Ring reversal capability on the hybrid Serial control interface External or software programmable receive gain, -3.5 or -7.0dB
MH89626C-02 MH89626C-04
ISSUE 3
May 1995
Ordering Information
38 Pin SIL Package 38 Pin SIL Package
0C to 70C
Description
The MH89626C SLIC provides all of the functions required to interface 2-wire off premise subscriber loops to a serial TDM, PCM, switching network of a modern PBX. The MH89626C is manufactured using thick film hybrid technology which offers high voltage capability, reliability and high density resulting in significant printed circuit board area saving of the line cards. A complete line card can be implemented with very few external components. The SLIC has a simple serial control interface to control the receive gain setting, relay drivers for ringing, and Tip/Ring reversal for DID operation.
Applications
* * * Off-Premise PBX Line Cards DID (Direct Inward Dial) Line Cards Central Office Line Cards
LGND TF TIP Tip Drive
VDD
VEE
LCA
AGND
RGND
VREF
F1i
C2i
2W/4W Conversion Current & Voltage Sensing Constant Current & Voltage Control Gain Adjust
MT8967 A-Law Filter/Codec
Do Di GS
SD2 SD3 SD0 SD1 Relay Driver 2
RING RF2 RF VBat
Ring Drive
Tip/Ring Reversed
8-Bit Shift Register SD4 Relay Driver 3
CS SDi
Auto Ring Line Supervision Trip Filter Relay Drive 1
LED
SHK
VAC
VRLY
RD1
RD2
RD3
SD5 SD6 SD7
Figure 1 - Functional Block Diagram
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MH89626C
TIP RING RF TF LPND VBat RF1 RF2 VEE AGND VDD IC VAC IC CS SHK LED LCA SD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VREF D1 C2i Do F1i IC IC IC GS IC SD7 SD6 SD5 IC VRLY RGND RD2 RD3 RD1
Preliminary Information
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 Name TIP RING RF TF LGND VBat RF1 RF2 VEE AGND VDD IC VAC Description Tip Lead: Connects to the TIP lead of the telephone line. Ring Lead: Connects to the Ring lead of the telephone line. Ring Feed. Tip Feed. Loop Ground: Return path for the battery (VBat) supply voltage. Connects to System Ground. Battery Supply Voltage: Normally -48V. Ring Feed 1: Ringing input. Ring Feed 2: Ringing output. Negative Supply Voltage. (-5V). Analog Ground: Analog and Digital Ground. Connects to system ground. Positive Supply Voltage. (+5V). Internal Connection. Battery AC Component (input). AC noise present in the VBat supply isolated from the DC components, can be applied to this pin to reduce longitudinal noise on TIP and RING. To implement this feature, connect a 0.1F 100V capacitor from VBat to VAC, and 1k resistor from VAC to AGND. This pin must be tied to AGND when not used. Internal Connection. Chip Select (Input): A TTL compatible digital input to enable the SDi to control all the functions of the driver. Switch Hook Detect (Output): A logic low indicates an off-hook condition. LED Drive (Output).: Drives an LED directly through an internal 2.2k resistor. A logic low indicates an off-hook condition. Loop Current Adjust (input): If this pin is left open, the constant current will be set at 23mA. The loop current can be adjusted by connecting a resistor to VEE.
14 15 16 17 18
IC CS SHK LED LCA
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Preliminary Information
Pin Description (Continued)
Pin # 19 20 21 22 23 24 Name SDi VRef Di C2i Do F1i Description
MH89626C
Serial Data in (input): A TTL compatible digital input. The 8-bit serial input enables the drivers. See Table 1 and Figure 3b. Voltage Reference (Input) +2.5V for the internal codec. Data in (Input). A TTL compatible digital input which accepts the 8-bit PCM word from the incoming PCM bus. Clock input (input). A TTl compatible digital input which accepts the 2048 kHz clock. Data Out (Output) A three state TTL compatible digital output which drives the 8-bit PCM word to the outgoing PCM bus. Synchronization input (Input). A TTL compatible, active low digital output input enabling the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i and provides frame and channel synchronization. See fig 3a. Internal Connection. Gain setting (Input). A logic `0' at this input will set the receiving gain to -7.0dB and a logic `1' will set the receiving gain to -3.5dB. If this pin is left open, the receiving gain can be set by SDi, bit 2. Internal Connection. Serial Data (Output). A TTL compatible output coming from the SDi, bit 7. Bit inverted. Serial Data (Output). A TTL compatible output coming from the SDi, bit 6. Bit inverted. Serial Data (Output). A TTL compatible output coming from the SDi, bit 5. Bit inverted. Internal Connection. Relay Positive Supply Voltage. Normally +5V. Connects to the relay coil and the relay supply voltage. Relay Ground. Return path for relay supply voltage. Relay Driver 2 (Output). Connects to a user provided external relay coil. A logic `0' from the SDi, bit 1 will activate this driver. This relay driver is typically used for system in-test. Relay Driver 3 (Output). Connects to a user provided external relay coil. A logic `0' from the SDi, bit 4 will activate this driver. This relay driver is typically used for system in-test. Relay Driver 1 (Output). Connects to a user provided external relay coil. A logic `0' from the SDi, bit 0 will activate this driver. This relay driver is typically used for ringing.
25-27 28
IC GS
29 30 31 32 33 34 35 36
IC SD7 SD6 SD5 IC VRLY RGND RD2
37
RD3
38
RD1
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MH89626C
Parameter 1 2 3 4 5 6 7 DC Supply Voltage DC Battery Voltages DC Ring Relay Voltage DC Reference Voltage AC Ring Generator Voltage DC Digital Input Voltage Storage Temperature GS,SDi,Di, C2i,F1i TS Symbol VDD VEE VBat VRLY VREF
Preliminary Information
Absolute Maximum Ratings*- All voltages are with respect to AGND unless otherwise specified.
Min -0.3 0.3 0.3 -0.3 -0.3 -0.3 -40 Max 7 -7 -65 7 VDD 150 VDD +125 Units V V V V V VRMS V C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
Parameter 1 2 3 4 5 6 DC Supply Voltage DC Battery Voltage DC Ring Relay Voltage DC Reference Voltage y AC Ring Generator Voltage Ringing Generator Frequency Operating Temperature TOP Symbol VDD VEE VBat VRLY VREF 2.488 22 0 Min 4.75 -4.75 -39.8 TYP* 5.0 -5.0 -48 5.0 2.500 90 25 25 Max 5.25 -5.25 -60 7.0 2.512 130 28 70 Units V V V V V VRMS Hz C Comments
LGND is connected to AGND y Temperature coefficient of VREF should be better than 100ppm/C
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Preliminary Information
DC Electrical Characteristics*
Characteristics 1 Supply and Battery Current
MH89626C
Sym IDD IEE IBat IBat PC 100 150 1500 2 VOL VOH VOL VOH IOL ICD VIL VIH IIL IIH IIL IIM IIH VOL VOH IOZ VIL VIH IIL IIH 4.0 0.1 0.8 2.4 10 10 -0.3 3.7 2.0 65 100 0.8 2.0 1 1 10 10 10 0.4 0 5 0.5 5.25 3.0 mW mW mW A V V V V mA mA V V A A A A V V mA V V A A VIL = 0V VIH = 5.0V VIL = 0V VIH = 5.0V VIL = 5.0V VIM = 0.5V VIH = 5.0V IOL = 1.6mA IOH = 0.1mA IOL = 2mA IOH = 2mA IOL = 1.1mA IOH = 0.7mA VOL = 1.0V RLoop = Open RLoop = 0 Min 5 5 Typ 12.5 11.7 23.5 1.5 Max 15 15 28 2 Units mA mA mA mA Test Comments
Short Loop Open Loop 2 Power Consumption On Hook (VBat) Powerdown (VDD and VEE) Off-Hook (VDD, VEE, VBat) VRef SHK LED DC Reference Voltage Mean Current Low Level Output Voltage High Level Output Voltage Low Level Output Voltagey High Level Output Voltage Sink Current, Relay to VDD Clamp Diode Current Low Level Input Voltage High Level Input Voltage GS Low Level Input Current High Level Input Current Low Level Input Current Intermediate Input Current High Level Input Current Low Level Output Voltage High Level Output Voltage Tri-State Leakage Current Low Level Input Current High Level Input Voltage Low Level Input Current High Level Input Current
RLoop = 0, LCA =Open RLoop = Open
0
3 4 5
6
RD1 RD2 RD3
7
8
9
SDi RD Do
10
11 12
SDi Di C2i F1i
* DC Electrical Characteristics are over Recommended Operating Conditions with VDD at + 5.0V + 5% unless otherwise stated. Typical figures are at 25C with nominal + 5V supplies and are for design aid only. x Supply current and power consumption characteristics are over Recommended Operating Conditions with VDD at 5.0V, VEE at -5.0V and V Bat at -48.0V. y The LED output consists of a 2.2K resistor in series with the SHK HCT output.
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MH89626C
Loop Electrical Characteristics*
Characteristics 1 Maximum AC Ringing Current Rejection Ring Trip Detect Time y Hook Switch Detect Time: Off-Hook to On-Hook On-Hook to Off-Hook Operating Loop Current Operating Loop Resistance Loop Current at Off-Hook z Detect Threshold IIP RIP Ish 18 0 0 7 10 22 Sym Min 33 Typ Max
Preliminary Information
Units mA
Test Comments 25Hz, VBat = -48V
2 3
100
125 20 20 50 1900 2300 13
ms ms ms mA mA LCA = Adjustable VBat = -39.8V VBat = -48V
4 5 6
* Loop Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal + 5V supplies and are for design aid only. x The SLIC can be loaded with an AC impedance as low as 4000 without generating a false SHK output. Since each REN represents 8k, the SLIC can drive a REN of 2 without generating a false SHK output. y This parameter is over Recommended Operating Conditions as well as the specified Operating Loop Resistance. z Off-Hook Detect (SHK) will be detected for loop lengths of 2900 or less.
AC Electrical Characteristics*
Characteristics 1 2- Wire input (200 + 560 // 0.1F) -2 Variant (200 + 680 // 0.1F) -4 Variant Return Loss at 2-Wire Sym Zin 720 813 14 18 14 40 46 16 20 16 PSRR 20 20 20 40 30 40 dB dB dB 51 40 32 65 65 36 24 24 Min Typ Max Units dB dB dB dB dB dB dB dB Test Comments
1020 Hz 1020 Hz 300 Hz 500-2000 Hz 3400 Hz 300-600 Hz 600-3400 Hz 300 Hz 500-2500 Hz 3400 Hz Ripple 50mV 1020 Hz
2
3 4
Longitudinal to Metallic Balance Transhybrid Loss
5
Power Supply Rejection Ratio at 2-wire and Do: VDD VEE VBat
* AC Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal +5V supplies and are for design aid only.
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Preliminary Information
AC Electrical Characteristics* - Transmit (A/D path)
Characteristics 1 2 3 Absolute Gain Default (codec odB) Transmit Gain Loss Distortion with frequency (relative to level at 1020Hz with codec at 0dB) 0.0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.25 -0.25 -0.5 -1.5 3.14 3.14 Sym Min -0.5 Typ 0 0 1.0 0.75 0.35 0.55 1.5 0.25 0.25 0.5 1.5 Max 0.5 Units dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm0
MH89626C
Test Comments Input -6dB 1020 Hz 0-200 Hz 200-300 Hz 300-400 Hz 400-600 Hz 600-2400 Hz 2400-3000 Hz 3000-3400 Hz Input 1020 Hz 0 to +3dBm -40 to 0dBm -50 to -40dBm -55 to -50dBm THD < 5% Input 1020Hz THD < 5% Input 1020Hz Input at 2-Wire 0 to -10dB -20dBm -30dBm -40dBm -50dBm Input at 2-wire -25dBm, 4.6 -72kHz 0dbm, 1020Hz 0dBm, 300 -3400 Hz
0.39
0.22
4
Gain variation with Input Level (relative to gain at 1020Hz with -6dBm input)
5 6
Signal Input Overload Level at 2-Wire Signal Output Overload Level at Do
7
Signal to Total Distortion Ratio at Do 35 33.8 28.8 19.5 14.5 dB dB dB dB dB -50 -40 -25 -41 -70 -64 dBm0 dBm0 dBm0 dB dBm0p
8
Out-of-Band Discrimination at Do: Signals in 4.6 -72 kHz band Signals in 300-3400 Hz band other than 1020 Hz Signals in 4.6 -72 kHz band Harmonic Distortion (2nd or 3rd Harmonic) at DSTo Idle Channel Noise at Do
9 10
Typical figures are at 25C with nominal +5V supplies and are for design aid only. * AC Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
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MH89626C
AC Electrical* - Receive (D/A) path
Characteristics 1 2 Absolute Gain (Codec 0dB, GS = 5V) Gain programmable Range GS = 5V GS = 0V Loss Distortion with Frequency (relative to level at 1020 Hz with codec at 0dB and GS = 5V) -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.25 -0.25 -0.5 -1.5 3.14 3.14 Sym Min -0.5 Typ 0.0 Max 0.5
Preliminary Information
Units dB
Test Comments Input -10dBm0 1020 Hz Input - 10dBm0 1020 Hz 1020 Hz Input -10dBm0 0-200 Hz 200-300 Hz 300-400 Hz 400-600 Hz 600-2400 Hz 2400-3000 Hz 3000-3400 Hz Input 1020 Hz 0 to +3dBm -40 to 0dBm -50 to -40dBm -55 to -55dBm THD < 5% Input 1020Hz THD < 5% Input 1020Hz Input at 2-Wire 0 to -20dB -30dBm -40dBm -50dBm Input at Di
-3.5 -7.0 1.0 0.75 0.35 0.55 1.5 0.25 0.25 0.5 1.5
dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm0
3
-0.09
-0.08
4
Gain Variation with Input Level (relative to gain to 1020Hz with -10dBm0 input)
5 6
Signal Input Overload Level at Di Signal Output Overload Level at 2-wire Signal Output to Total Distortion Ratio at 2-Wire
7
35 32.9 24.9 19.9
dB dB dB dB
8
Out-of-Band Discrimination at 2-Wire: Signals in 4.6 -72 kHz band Signals in 300-3400 Hz band other than 1020 Hz Signals in 4.6 -72 kHz band Harmonic Distortion (2nd or 3rd Harmonic) at 2-Wire Idle Channel Noise at 2-Wire -73 -73
-50 -40 -25 -41
dBm dBm dBm dB
-25dBm0, 4.6 -72kHz 0dBm0, 1020 Hz 0dBm0, 300-3400 Hz
9 10
-67 -67
dBmp dBmp
Gain Setting -3.5dB -7dB
* AC Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal +5V supplies and are for design aid only.
2-292
Preliminary Information
Loop Electrical Characteristics
Characteristics 1 2 3 4 5 6 7 D I G I T A L Clock Frequency Clock Rise Time Clock Fall Time Clock Duty Cycle Chip Enable Rise Time Chip Enable Fall Time Propagation Delay Clock to Output Enable Input Setup Time Input Hold Time C2i C2i C2i C2i F1i F1i Do tER tEF tPZL tPZH tISH tISL tIH 25 0 60 Sym
fC
MH89626C
Min 2.046 Typ* 2.048 Max 2.05 50 50 40 50 60 100 100 122 122 Units MHz ns ns % ns ns ns ns ns ns ns RL = 10k to VCC CL = 100pF Test Comments
tCR tCF
8 9
Di Di
* Typical figures are at 25C with nominal +5V supplies. For design aid only: not guaranteed and not subject to production testing.
Bit
0 1 2 3 4 5 6 7
Name SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
Description When Logic `0' activates relay driver 1 to apply ringing to the line When logic `0' activates relay driver 2. Normally used for in-test When logic `0' it will set the receive gain to -7.0dB When logic `1' it will set the receive gain to -3.5dB When logic `0' reverses the TIP and RING. When logic `0' activates relay driver 3. Normally used for out-test The output of the serial data stream SDi, bit 5. Bit inverted The output of the serial data stream SDi, bit 6. Bit inverted The output of the serial data stream SDi, bit 7. Bit inverted Table 1 - Control of SLIC Functions through SD
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MH89626C
Functional Description
The MITEL MH89626C OPS SLIC (Off-Premise Subscriber Line Interface Circuit) provides a complete interface between an off-premise telephone line and a digital switching system. All BORSCHT functions are provided requiring only a few external components. The input impedance conforms with Chinese standard requirements.
Preliminary Information
TIP/RING Reversal
For a Direct Inward Dialling (DID) operation, the MH89626C provides a TIP and RING reversal function on the hybrid. This built-in line polarity reversal capability will eliminate the use of an external bulky mechanical relay and provides fast and reliable Tip and Ring reversed function. The serial control stream, SDi, bit 3 at logic low will reverse the polarity of the Tip and Ring. Refer to Table 1 for control of the SLIC functions.
Overvoltage Protection
The MH89626C is protected from short term (20ms) transients (+250V) between TIP and RING, TIp and Ground, and RING and Ground. However, if the MH89626C is used in conjunction with MH80626C, protection sip, it will meet all CCITT K.20 requirements. The applications circuit is shown in Figure 2. The MH80626C has two battery feed resistors (50 ohms) and one ringing feed resistor (560 ohms), that are required to be used with the MH89626C as a complete line interface. All resistors on the hybrid are specially designed to withstand high power. The two battery feed resistors are accurately trimmed to achieve good longitudinal balance. Two fuses and current limited resistors (5 ohms) are provided on the hybrid for lightning and high voltage surge protection.
Ringing
The ringing insertion circuitry has the capability to provide ringing voltage to a telephone set by simply adding an external relay, ring generator. The serial control stream, SDi, bit 0 at logic low will activate the Refer to Table 1 for the control of SLIC functions.
Supervision
The loop detection circuit determines whether a low enough impedance is across Tip and Ring to be recognized as an off-hook condition. When an off-hook condition occurs, the SHK and the LED outputs toggle to a low level. These outputs also toggle with incoming dial pulses. During applied ringing, the loop detection circuit engages a ringing filter. This filter prevents a false off-hook detection due to the current associated with the AC ringing voltage as well as current transients that occur when the ringing voltage is switched in and out. The Ring trip detection circuitry deactivates the ring driver after an off-hook condition is detected.
Battery Feed
The MH89626C powers the telephone set with constant DC loop current for short lines and automatically reverts to constant voltage for long lines. If the LCA pin is left open, the constant current is set at 23 mA. The Constant current can also be set by adding a resistor connected fro the LCA pin to VEE. The resistance (R) can be calculated as: 147.2 - ILoop (0.0001176 X ILoop) - 0.002586 Where ILoop is the desired constant loop current in mA, and R is the resistance from pin LCA to pin VEE in ohms.
Transmit and Receive Gain
The Transmit Gain (Tip-Ring to Do) is fixed at 0dB. The Receive Gain (Di to Tip-Ring) is programmable in -3.5 or -7.0dB, either using software (SDi, bit 2) or external hardware (GS pin).
R=
R(k) ILoop (mA)
348K 25.0
200K 27.1
80K 34.0
50K 40.2
30K 49.7
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Preliminary Information
MH89626C
MH80626C
TOUT
5 6
K1A D1 D3 1 4 3 2 D2 D4
C1 to other circuit Heat sink 9oC/W
MH89626C
24 TIP TF RF RING Do Di GS SDi 21 28 19 F1i VRef C2i 20 22 23
Test Out
Test In 1
T TF RF R
14 12 7
Tip K3A K2A
TIN 8 ROUT 20 RIN RF2 RF1 18 16 K1B R1 R2
-48V
Q1
8 7 30 31 32 38 +5V K1 RELAY 36 K2 RELAY PTC 371 K3 RELAY 34
RF2 RF1 SD7 SD6 SD5 RD1 RD2
Ring
CS 17 LED SHK VAC LGND 5 6 VBat 18 LCA 16
15
K3B
K2B
13
90VRMS 25Hz -48V Components D1,D2,D3,D4 IN4004 Q1 = FET BUZ 22 or equivalent R1 = 10k +5% 1/4W R2 = 1k + 5% 1/4W C1 = 0.01F + 10% 100V PTC = 55, 50mA 290V TISP
-48V
RD3 VRLY VDD 31 VEE 9 AGND 30 RGND 18
+5V
-5V
Figure 3 - Application Circuit
C2i F1i
tPHZ tES tES Do tPZH tPZL tPLH tPHL
Di tISL tIH tISH
Figure 4a - Control Timing Diagram
2-295
MH89626C
Preliminary Information
C2i
CS
SD1
b7
b6
b5
b2
b1
b0
Figure 4b -Control Timing Diagram
0.12 Max (3.0 Max) Side View 0.58+0.02 (14.7+0.5)
3.80 + 0.015 (9.652 + 1.4)
1234
37 38
0.010 + 0.002 (0.25 + 0.05) 0.27 Max (6.9 Max)
* 0.05 + 0.01 (1.3 + 0.5) Notes: 1) Not to scale 2) Dimensions in inches). 3) (Dimensions in millimetres). *Dimensions to centre of pin & tolerance non accumulative. * 0.25 + 0.02 (6.4 + 0.05) 0.020 + 0.005 (0.51 + 0.13) * * 0.18 + 0.02 (4.6 + 0.5)
0.100 + 0.010 (2.54 + 0.26)
Figure 5 - Mechanical Data
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